At Nanosystems JP Inc., the processes quantum hardware groups struggle to source, deep silicon etching, glass vias, indium and gold bumping, UHV-compatible AuSn, wafer bonding, fused silica optics, ion implantation, run as one flow, from single wafers, managed end to end by a dedicated project manager. This page maps five quantum platforms to the services that build them, and the four packaged offerings we ship most.
Surface traps want thick gold electrodes, deep trenches for optical access, backside routing so wirebonds stay out of laser paths, and through-holes for beams. That is our DRIE (Bosch, 50:1), TGV, thick Au plating, and Ti/Au patterning in one program, with AuSn as the fluxless, low-outgassing die attach inside the vacuum can.
Thick electroplated Au electrode layers with Ti/Au lift-off patterning, backside redistribution, and double-side lithography so control wiring leaves the optical plane clear.
DRIE trenches and loading slots at 50:1 aspect ratio, plus through-substrate laser access holes, in Si or via unfilled through-glass vias.
AuSn multilayer stacks for fluxless die attach on carriers, no flux, no organics, nothing to outgas next to the trap.
Vapor and vacuum cells are glass-and-silicon stacks: etched Si bodies, anodic and adhesive bonding to glass, and patterned metal on transparent substrates. Our fused silica program and micron-scale metal meshes on sapphire are already neutral-atom optics parts in all but name.
DRIE cavities in silicon bonded to glass windows, anodic, adhesive, or eutectic per your stack, as sealed bodies or open halves.
Ti/Au, apertures, and fine metal meshes patterned on fused silica and sapphire, double-side where the optics demand it.
Micron-scale apertures and beam-defining features by lift-off on transparent substrates, aligned front to back.
Waveguide-era quantum hardware runs on our photonics stack: SiN and low-temperature dielectrics, AR stacks, edge coupling and V-grooves, CMP planarization, and glass TGV interposers for driver and detector integration. These are the inquiries we already receive.
SiN and SiO₂ films at photonics-safe temperatures, CMP planarization below 0.5nm Ra, and facet-respecting dicing.
Glass TGV interposers, Ø20µm standard vias with void-free Cu fill, for cryo drivers, detectors, and fan-out.
Edge coupling notches, V-grooves, and fiber-attach geometries etched and diced to your coupling design.
Defect engineering is ion implantation plus activation annealing plus fine lithography, on Si and SiC. Our SiC substrate experience and Ni-based lift-off contact work transfer directly; diamond programs are discussed per inquiry.
Ion implantation with species and dose per your defect recipe, followed by RTA or furnace activation in the same flow.
SiC substrates procured and processed, contacts by lift-off, annealing, and the handling wide-bandgap wafers require.
Alignment marks, mesas, and contact patterns at stepper accuracy so single defects can be found again.
The segment closest to real volume and least served by incumbent foundries. MEMS alkali vapor cells are DRIE cavities plus anodic or adhesive glass bonding plus windows, a flow our microfluidics and bonding lines already run. See the dedicated MEMS vapor cell page.
Si cavity bodies bonded to glass, delivered as open halves or bonded unfilled bodies; alkali filling by arrangement.
Polished, patterned windows with apertures and coatings coordinated through the fused silica program.
From single prototype pairs to repeat lots on a fixed recipe, the scaling path OPM and clock programs need.
Every platform above routes into the same shared process core, and out of it come the four packaged offerings below.
Each is a page of its own, with specs, and each orders from a single wafer.
Research lots are our standard offer, not a favor. Prototype on one wafer, publish, then repeat on the same recipe.
Deep etch, glass vias, indium, AuSn, bonding, implantation: the steps that usually mean five different quotes run here as one program.
Fluxless metallurgies, low-outgassing choices, and material selections made for vacuum cans and cryostats, not just reflow ovens.
Fused silica, sapphire, and glass are first-class substrates in this flow, patterned, drilled, bonded, and diced routinely.
Mixed-platform programs stay coherent, managed end to end by a dedicated project manager from RFQ to shipment.
Every offering above links to a full specification page, so your design review starts from numbers, not adjectives.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.