At Nanosystems JP Inc., we fabricate high-lead solder bumps, 95Pb/5Sn and 97Pb/3Sn, by evaporation and lift-off: the original C4 flip-chip metallurgy, kept alive where decades of qualified fatigue and reliability data matter more than anything newer. For space, defense, and legacy-system programs operating under the applicable RoHS exemptions for high-melting-temperature solders. 4-12 inch wafers, from a single wafer.
Why high-Pb survives
Mostly displaced by plated SnAg and RoHS, high-lead C4 persists where its fatigue behavior and alpha-emission characteristics are already qualified into flight and defense hardware, and re-qualifying anything else costs more than the parts. For new low-temperature designs, indium and AuSn are the modern companions on the same flow.
High-lead solder bumps were the first flip-chip interconnect, evaporated through shadow masks decades before plating took over. Three reasons keep them in production for a narrow, demanding customer base.
No bump metallurgy has a longer reliability record. Thermal-fatigue models, creep behavior, electromigration limits, and failure statistics for high-Pb C4 joints were established across decades of mainframe and hi-rel production, and that body of qualification is exactly what space and defense programs are certified against. Changing the metallurgy means re-qualifying the system; keeping it means sourcing the process, which is where we come in.
Melting around 310-320°C, high-Pb joints stay solid through every SnAg reflow below them, serving as the first-level interconnect in multi-step assemblies the same way they did in the original C4 architecture. The soft, compliant lead matrix also absorbs thermal-cycling strain, the fatigue behavior those decades of data describe.
Solders containing 85% or more lead by weight fall under the long-standing RoHS exemption for high-melting-temperature solders, which is why the metallurgy remains legally available for the aerospace, defense, and industrial categories that need it. For radiation-sensitive electronics, low-alpha lead source material is available on request to control alpha-particle soft-error rates.
Historic C4 lines evaporated Pb and Sn through molybdenum shadow masks. We run the same physics through modern lift-off resist, stacked Pb/Sn layers evaporated to composition and lifted off, with photolithographic registration the shadow masks never had.
| Parameter | 95Pb/5Sn | 97Pb/3Sn |
|---|---|---|
| Melting Range | ~310°C | ~320°C |
| Wafer Sizes | 4 inch (100mm), 6 inch (150mm), 8 inch (200mm), 12 inch (300mm) | |
| Deposition | Stacked Pb/Sn evaporation; composition by layer thickness ratio | |
| Patterning | Lift-off, stepper registration ±0.5µm | |
| Bump Height | 3-10µm as deposited | |
| Minimum Pitch | ~25µm typical (C4-class geometries) | |
| Base Metallurgy | Cr / Cr-Cu / Cu / Au classic BLM, or Ti/Ni/Au | |
| Composition Verification | Layer thickness ratio at deposition | |
| Low-Alpha Material | Low-alpha Pb source on request, with certification | |
| Regulatory Scope | Applications under RoHS exemptions for solders ≥85% Pb; confirmed at RFQ | |
| Inspection | Profilometry + SEM standard; shear on request | |
| Minimum Lot | From 1 wafer; rebuild and last-time-buy lots supported | |
Flip-chip interconnect for satellite and launch hardware qualified around high-Pb metallurgy, where the existing thermal-fatigue and vacuum heritage is the reason the alloy is specified, and re-qualification is the cost being avoided.
High-reliability flip-chip and die attach for defense and avionics programs running under long-established qualification baselines, supplied with the process documentation those programs audit.
When an original C4 source disappears, we reproduce the evaporated high-Pb process from your specifications, single wafers to bridge lots, keeping certified systems supplied without redesign.
First-level joints that must stay solid through downstream SnAg assembly, the ~310-320°C melting range doing the same hierarchy job it did in the original C4 architecture.
Low-alpha lead sourcing for electronics where alpha-particle soft errors matter, memory-adjacent die and instrumentation, delivered with material certification per program.
Single-wafer runs reproducing qualified legacy stacks for failure analysis, reliability studies, and heritage-process research, with modern metrology on a historical metallurgy.
High-Pb C4 is an evaporated metallurgy, and evaporation with lift-off is the discipline our whole bump family runs on. No process translation, no plating compromise.
The classic Cr / Cr-Cu / Cu / Au BLM and stacked Pb/Sn evaporation, with stepper lithography in place of shadow masks, the original physics at modern accuracy.
Rebuild programs need one to a few wafers with full documentation, not volume commitments. From 1 wafer is our standard offer, not an exception.
Process specifications and inspection data packaged for hi-rel and defense review, the paperwork half of legacy reproduction.
Standard and low-alpha lead source material quoted per program with certification, so the procurement problem arrives solved.
High-Pb, AuSn, indium, gold, and UBM share lithography and evaporation, managed end to end by a dedicated project manager, so mixed-metallurgy programs stay in one place.
Share your process requirements, substrate, and production volume. A Nanosystems JP Inc. engineer will respond within 24 hours. Full quote typically within 7-10 business days, subject to project complexity and NDA requirements.